View MPC823EELD_385020.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Order this document by MPC823EELE/D Rev 0
MPC823e AC Electrical Specifications
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC823e. Note: Visit our website at www.motorola.com if you are using a frequency other than 25, 40, or 50MHz. Our website contains a spreadsheet that you can use to calculate the timing for your specific system frequency.
This device contains circuitry protecting against damage from high-static voltage or electrical fields. However, it is advised that precautions be taken to avoid application of any voltages higher than the maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC).
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. PowerPC is a registered trademark of IBM Corp. and is used by Motorola under license from IBM Corp. I2C is a registered trademark of Philips Corporation.
O 2000 Motorola, Inc.All Rights Reserved.
MAXIMUM RATINGS (GND = 0V)
RATING Supply Voltage SYMBOL VDDH VDD KAPWR VDDSYN Input Voltage (JTAG and GPIO) Input Voltage (All other pins) Operating Temperature VIN VIN TA VALUE -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 5.8 -0.3 to 3.3 0 to 70u or -40u to 85u -55 to +150 UNIT V V V V V V uC
Storage Temperature Range NOTES: 1.
TSTG
uC
Functional operating conditions are given in DC Electrical Characteristics (VCC = 3.0 3.6 V). Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. CAUTION: The JTAG and GPIO input voltages cannot be more than 2.5 V greater than supply voltage, this restriction applies also on Opower-onO as well as on normal operation. 5 Volt friendly inputs are inputs that tolerate 5 volts for JTAG and GPIO pins.
2. 3.
THERMAL CHARACTERISTICS
CHARACTERISTIC Thermal Resistance for BGA SYMBOL qJc VALUE ~30 UNIT C/W
2
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in C can be obtained from TJ = TA + (PD qJA) where TA = qJA = PD = PINT = PI/O = Ambient Temperature, C Package Thermal Resistance, Junction to Ambient, C/W PINT + PI/O IDD x VDD, WattsNChip Internal Power Power Dissipation on Input and Output PinsNUser Determined (1)
For most applications PI/O < 0.3 PINT and can be neglected. If PI/O is neglected, an approximate relationship between PD and TJ is: PD = K O (TJ + 273C) (2)
Solving equations (1) and (2) for K gives K= PD (TA + 273C) + qJA PD
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
Layout Practices
Each VCC pin on the MPC823e should be provided with a low-impedance path to the boardOs supply. Each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 mF bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inch per capacitor lead. A four-layer board that employs two inner layers as VCC and GND planes should be used. All output pins on the MPC823e have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
3
DC ELECTRICAL CHARACTERISTICS (VCC = 3.0 - 3.6 V)
CHARACTERISTIC Input High Voltage (for JTAG and GPIO) Input High Voltage (all other pins) Input Low Voltage EXTAL and EXTCLK Input High Voltage Input Leakage Current, VIN = 5.5 V Hi-z (Off State) Leakage Current, VIN = 3.5V Signal Low Input Current, VIL = 0.8 V Signal High Input Current, VIH = 2.0 V Output High Voltage, IOH = 2.0 mA, VDDH = 3.0V Except XTAL, XFC, and Open-Drain Pins Output Low Voltage IOL = 2.0 mA CLKOUT IOL = 3.2 mAA[6:31], TSIZ0/REG, TSIZ1, D(0:31), DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1], IP_B2/ IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/ VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, USBRXD/PA15, RXD2/ PA13, SMRXD2/L1TXDA/PA9, SMTXD2/L1RXDA/PA8, IRQ4/KR/ SPKROUT, TIN1/L1RCLKA/BRGO1/CLK1/PA7, TIN3/L1RCLKB/ TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TIN4/ L1TCLKB/TOUT2/CLK4/PA4, LCD_A/SPISEL/PB31, SPICLK/ PB30, SPIMOSI/PB29, BRGO3/SPIMISO/PB28, BRGO1/I2CSDA/ PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/L1RXDB/ PB24, SMSYN1/SDACK1/L1TSYNCB/PB23, SMSYN2/SDACK2/ L1RSYNCB/PB22, LCD_B/L1ST1/PB19, L1ST2/RTS2/PB18, LCD_C/L1ST3/PB17, L1ST4/L1RQA/PB16, L1ST5/L1TXDB/ DREQ1/PC15, L1ST6/RTS2/DREQ2/PC14, L1ST7/PC13, L1ST8/ L1RQA/PC12, USBRXP/PC11, USBRXN/TGATE1/PC10, CTS2/ PC9, TGATE1/CD2/PC8, USBTXP/PC7, USBTXN/PC6, SDACK1/ L1TSYNCA/PC5, L1RSYNCA/PC4, LD8/VD7/PD15, LD7/VD6/ PD14, LD6/VD5/PD13, LD5/VD4/PD12, LD4/VD3/PD11, LD3/VD2/ PD10, LD2/VD1/PD9, LD1/VD0/PD8, FRAME/VSYNC/PD5, LCD_AC/LOE/BLANK/PD6, LD0/FIELD/PD7, LOAD/HSYNC/PD4, SHIFT/CLK/PD3 IOL = 5.3 mABDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/ CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR, WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/ GPL_A1/GPL_B1, GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/ GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1, OP2/MODCK1/STS, OP3/MODCK2/DSDO IOL = 7.0 mA USBOE/PA14, TXD2/PA12 IOL = 8.9 mATS, TA, TEA, BI, BB, HRESET, SRESET NOTE: Input pin voltage specifications are VCC = +4 V or 5.8 V, whichever is less. AC timings are based on a 50 p| load. SYMBOL VIH VIH VIL VIHC IIN IOZ IL IH VOH VOL 2.4 N MIN 2.0 2.0 GND 0.7*(VCC) N N MAX 5.5 3.6 0.8 VCC+0.3 10 10 10 10 N 0.5 UNIT V V V V A A A A V V
4
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
2.0V CLKOUT 0.8V A B 2.0V OUTPUTS 0.8V 2.0V 0.8V 0.8V
2.0V
A
B 2.0V OUTPUTS 0.8V 2.0V 0.8V
C
D
2.0V INPUTS 0.8V
2.0V 0.8V
C 2.0V INPUTS 0.8V
D 2.0V 0.8V
A = MAXIMUM OUTPUT DELAY SPECIFICATION B = MINIMUM OUTPUT HOLD TIME
C = MINIMUM INPUT SETUP TIME SPECIFICATION D = MINIMUM INPUT HOLD TIME SPECIFICATION
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
5
EXTERNAL BUS ELECTRICAL CHARACTERISTICS
Table 1. Bus Operation Timing
25MHz NUM B1 B1a B1b B1c B1d B1e B1f B1g B1h B2 B3 B4 B5 B6 B7 B7a B7b B8 B8a B8b B9 B10 B11 CLKOUT Period EXTCLK to CLKOUT Phase Skew (EXTCLK>15MHz and MF 2) EXTCLK to CLKOUT Phase Skew (EXTCLK>10MHz and MF 10) CLKOUT Phase Jitter (EXTCLK>15MHz and MF2) CLKOUT Phase Jitter (EXTCLK>10MHz and MF10) CLKOUT Frequency Jitter (MF<10) CLKOUT Frequency Jitter (10500) Frequency Jitter on EXTCLK Clock Pulse Width Low Clock Pulse Width High CLKOUT Rise Time CLKOUT Fall Time N/A (Used on Interactive Spreadsheet) CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3) Invalid CLKOUT to TSIZ(0:1),REG, RSV, AT(0:3),BDIP, PTR Invalid CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2), IWP(0:2), LWP(0:1), STS Invalid CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3) Valid CLKOUT to TSIZ(0:1),REG, RSV, AT(0:3), BDIP, PTR Valid CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS Valid CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1),REG, RSV, AT(0:3), PTR Hi Z N/A CLKOUT to TS, BB Assertion 10 2.5 10 2.5 10 19 11 19 11 24 5 2.5 5 2.5 5 12.25 9.25 13 11 21 5 2.5 5 2.5 5 12.25 9.25 12 11 19 ns ns ns ns ns 10 10 10 10 10 10 10 N N N 19 19 19 19 5 5 5 5 5 5 5 N N N 13 13 13 13 5 5 5 5 5 5 5 N N N 12 12 12 12 ns ns ns ns ns ns ns CHARACTERISTIC MIN 40 -0.9 -2.3 -0.6 -2 N N N N 16 16 N N MAX N 0.9 2.3 0.6 2 0.5 2 3 0.5 N N 4 4 MIN 25 -0.9 -2.3 -0.6 -2 N N N N 10 10 N N MAX N 0.9 2.3 0.6 2 0.5 2 3 0.5 N N 4 4 MIN 20 -0.9 -2.3 -0.6 -2 N N N N 8 8 N N MAX N 0.9 2.3 0.6 2 0.5 2 3 0.5 N N 4 4 ns ns ns ns ns % % % % ns ns ns ns 40MHz 50MHz UNIT
to TA, BI Assertion (when driven B11a CLKOUTController or PCMCIA Interface) by the Memory B12 CLKOUT to TS, BB Negation
to TA, BI Negation (when driven B12a CLKOUTController or PCMCIA Interface) by the Memory B13 CLKOUT to TS, BB Hi Z
6
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 1. Bus Operation Timing (Continued)
25MHz NUM CHARACTERISTIC MIN B13a CLKOUT to TA, BI Hi Z (When Driven by the Memory Controller or PCMCIA Interface) B14 B15 B16 CLKOUT to TEA Assertion CLKOUT to TEA Hi Z TA, BI Valid to CLKOUT (Setup Time) 2.5 2.5 2.5 9.75 11 8.5 1 2 6 2 4 2 10 N 10 14 3 8 18 N 3 48 58 N 10 N MAX 15 11 15 N N N N N N N N N 20 10 20 25 10 N N 11 11 N N 11 20 20 MIN 2.5 2.5 2.5 9.75 10 8.5 1 2 6 2 4 2 5 N 5 7 2 3 8 N 2 23 28 N 5 N MAX 15 11 15 N N N N N N N N N 13 8 13 16 8 N N 9 9 N N 9 13 13 MIN 2.5 2.5 2.5 9.75 10 8.5 1 2 6 2 4 2 5 N 5 7 2 3 8 N 2 23 28 N 5 N MAX 16 10 15 N N N N N N N N N 13 8 13 16 8 N N 9 9 N N 9 13 13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40MHz 50MHz UNIT
B16a TEA, KR, RETRY Valid to CLKOUT (Setup Time) B16b BB, BG, BR Valid to CLKOUT (Setup Time) B17 CLKOUT to TA, TEA, BI , BB, BG, BR Valid (Hold Time)
B17a CLKOUT to KR, RETRY Valid (Hold Time) B18 B19 B20 B21 B22 D(0:31), DP(0:3) Valid to CLKOUT Rising Edge (Setup Time) CLKOUT Rising Edge to D(0:31), DP(0:3) Valid (Hold Time) D(0:31), DP(0:3) Valid to CLKOUT Falling Edge (Setup Time) CLKOUT Falling Edge to D(0:31), DP(0:3) Valid (Hold Time) CLKOUT Rising Edge to CS Asserted -GPCM- ACS = 00
B22a CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 10, TRLX = 0 B22b CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 0 B22c B23 B24 CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 1 CLKOUT Rising Edge to CS Negated -GPCM-Read Access GPCM-Write Access, ACS=00, TRLX=0, CSNT=0 A(6:31) to CS Asserted -GPCM- ACS = 10, TRLX = 0
B24a A(6:31) to CS Asserted -GPCM- ACS = 11, TRLX = 0 B25 B26 B27 CLKOUT Rising Edge to OE, WE(0:3) Asserted CLKOUT Rising Edge to OE Negated A(6:31) to CS Asserted -GPCM- ACS = 10, TRLX = 1
B27a A(6:31) to CS Asserted -GPCM- ACS = 11, TRLX = 1 B28 CLKOUT Rising Edge to WE(0:3) Negated -GPCM-Write Access CSNT = O0O
Edge to B28a CLKOUT FallingO0O, CSNTWE(0:3) Negated -GPCM-Write Access TRLX = = O1O, EBDF=0 -GPCM-Write Access CLKOUT Falling Edge to CS B28b TRLX = O0O, CSNT = O1O, ACS Negated ACS=O11O, EBDF = 0 = O10O or
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
7
Table 1. Bus Operation Timing (Continued)
25MHz NUM CHARACTERISTIC MIN B28c CLKOUT Falling Edge to WE(0:3) Negated -GPCM-Write Access TRLX = O0O, CSNT = O1O, EBDF=1 14 N 8 18 8 18 58 58 12 12 52 52 8 18 MAX 25 25 N N N N N N N N N N N N MIN 7 N 3 8 3 8 28 28 5 5 24 24 3 8 MAX 16 16 N N N N N N N N N N N N MIN 7 N 3 8 3 8 28 28 5 5 24 24 3 8 MAX 16 16 N N N N N N N N N N N N ns ns ns ns ns ns ns ns ns ns ns ns ns 40MHz 50MHz UNIT
-GPCM-Write Access CLKOUT Falling Edge to CS B28d TRLX = O0O, CSNT = O1O, ACS Negated ACS=O11O, EBDF = 1 = O10O or B29 WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access, CSNT = O0O
Negated to D(0:31), DP(0:3) Hi B29a WE(0:3) TRLX = O0O, CSNT = O1O, EBDF =Z -GPCM- Write Access, 0 to D(0:31), DP(0:3) Hi Z B29b CS NegatedTRLX = O0O & CSNT = O0O -GPCM- Write Access, ACS = O00O, B29c CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access, TRLX = O0O, CSNT = O1O, ACS = O10O or ACS=O11O, EBDF = 0
WE(0:3) Negated to D(0:31), DP(0:3) Hi B29d Access, TRLX = O1O, CSNT = O1O, EBDF =Z -GPCM- Write 0 to D(0:31), DP(0:3) Hi B29e CS NegatedCSNT = O1O, ACS = O10O Z -GPCM- Write Access, TRLX = O1O, or ACS=O11O, EBDF = 0 B29f WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access, TRLX = O0O, CSNT = O1O, EBDF = 1
to D(0:31), DP(0:3) Hi B29g CS NegatedCSNT = O1O, ACS = O10O Z -GPCM- Write Access, TRLX = O0O, or ACS=O11O, EBDF = 1 WE(0:3) Negated to D(0:31), DP(0:3) Hi B29h Access, TRLX = O1O, CSNT = O1O, EBDF =Z -GPCM- Write 1 B29i B30 CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access, TRLX = O1O, CSNT = O1O, ACS = O10O or ACS=O11O, EBDF =1 CS, WE(0:3) Negated to A(6:31) invalid -GPCM- Write Access.
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access, A(6:31) Invalid B30a TRLX=O0O, CSNT = '1O. CS Negated to ACS = 10,ACS-GPCMWrite Access, TRLX=O0O, CSNT = '1O, = =O11O, EBDF = 0 WE(0:3) Negated to A(6:31)Invalid -GPCM- Write Access, A(6:31)Invalid B30b TRLX=O1O, CSNT = '1O. CS Negated toACS = 10,ACS-GPCMWrite Access, TRLX=O1O, CSNT = '1O, = =O11O, EBDF = 0 B30c WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access, TRLX=O0O, CSNT = '1O. CS Negated to A(6:31) Invalid -GPCMWrite Access, TRLX=O0O, CSNT = '1O, ACS = 10 ,ACS = =O11O, EBDF = 1
58
N
28
N
28
N
ns
12
N
4
N
4
N
ns
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access, A(6:31) Invalid B30d TRLX=O1O, CSNT = '1O. CS Negated to ACS = 10,ACS-GPCMWrite Access, TRLX=O1O, CSNT = '1O, = =O11O, EBDF = 1 B31 CLKOUT Falling Edge to CS valid as requested by CST4 in the corresponding word of the UPM
52
N
24
N
24
N
ns
1.5
10
1.5
8
1.5
8
ns
8
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 1. Bus Operation Timing (Continued)
25MHz NUM CHARACTERISTIC MIN requested B31a CLKOUT Falling Edge to CS valid asEBDF = 0 by CST1 in the corresponding word of the UPM, CLKOUT Rising Edge to CS valid as B31b the corresponding word of the UPM requested by CST2 in B31c CLKOUT Rising Edge to CS valid as requested by CST3 in the corresponding word of the UPM 10 1.5 10 10 1.5 10 1.5 10 10 1.5 10 8 18 28 8 18 28 8 6 1 9 MAX 20 10 20 25 10 20 10 20 25 10 20 N N N N N N N N N N MIN 5 1.5 5 5 1.5 5 1.5 5 5 1.5 5 3 8 13 3 8 13 3 6 1 7 MAX 13 8 13 16 8 13 8 13 16 8 13 N N N N N N N N N N MIN 5 1.5 5 5 1.5 5 1.5 5 5 1.5 5 3 8 13 3 8 13 3 6 1 7 MAX 13 8 13 16 8 13 8 13 16 8 13 N N N N N N N N N N ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40MHz 50MHz UNIT
requested B31d CLKOUT Falling Edge to CS valid asEBDF = 1 by CST1 in the corresponding word of the UPM, B32 CLKOUT Falling Edge to BS valid as requested by BST4 in the corresponding word of the UPM
requested B32a CLKOUT Falling Edge to BS valid asEBDF = 0 by BST1 in the corresponding word of the UPM, CLKOUT Rising Edge B32b corresponding word ofto BS valid as requested by BST2 in the the UPM B32c CLKOUT Rising Edge to BS valid as requested by BST3 in the corresponding word of the UPM
requested B32d CLKOUT Falling Edge to BS valid asEBDF = 1 by BST1 in the corresponding word of the UPM, B33 CLKOUT Falling Edge to GPL valid as requested by GxT4 in the corresponding word of the UPM
GPL B33a CLKOUT Rising Edge toof the valid as requested by GxT3 in the corresponding word UPM B34 A(6:31) and D(0:31) to CS valid as requested by CST4 in the corresponding word of the UPM
to B34a A(6:31) and D(0:31) of CS valid as requested by CST1 in the corresponding word the UPM to B34b A(6:31) and D(0:31) of CS valid as requested by CST2 in the corresponding word the UPM B35 A(6:31) and D(0:31) to BS valid as requested by BST4 in the corresponding word of the UPM
A(6:31) and D(0:31) to BS B35a corresponding word of the valid as requested by BST1 in the UPM to BS B35b A(6:31) and D(0:31) of the valid as requested by BST2 in the corresponding word UPM B36 B37 B38 B39 A(6:31) and D(0:31) to GPL valid as requested by GxT4 in the corresponding word of the UPM UPWAIT Valid to CLKOUT Falling Edge CLKOUT Falling Edge to UPWAIT Valid AS Valid to CLKOUT Rising Edge
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
9
Table 1. Bus Operation Timing (Continued)
25MHz NUM CHARACTERISTIC MIN B40 B41 B42 B43 A(6:31), TSIZ(0:1), RD/WR, BURST, Valid to CLKOUT Rising Edge TS Valid to CLKOUT Rising Edge (Setup Time) CLKOUT Rising Edge to TS Valid (Hold Time) AS Negation to Memory Controller Signals Negation 9 9 2 N MAX N N N 13 MIN 7 7 2 N MAX N N N 13 MIN 7 7 2 N MAX N N N 13 ns ns ns ns 40MHz 50MHz UNIT
NOTES: 1. 2. 3. The timing for BR output is relevant when the MPC823e is selected to work with the external bus arbiter. The timing for BG output is relevant when the MPC823e is selected to work with the internal bus arbiter. The setup times required for TA, TEA and BI are relevant only when they are supplied by an external device (and not when the memory controller or the PCMCIA interface drive them). The timing required for BR input is relevant when the MPC823e is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC823e is selected to work with the external bus arbiter. The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only under control of the UPM in the memory controller. The timing B30 refers to CS when ACS = O00O and to WE(0:3) when CSNT = O0O. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specied in B37 and B38 are specied to enable the freeze of the UPM output signals. The AS signal is considered asynchronous to the CLKOUT signal.
4. 5. 6. 7. 8.
CLKOUT
B1
B3 B2 B1
B4
B5
Figure 1. External Clock Timing Diagram
10
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B8 B9 B7
OUTPUT SIGNALS
B8a B9 B7a
OUTPUT SIGNALS
B8b
B7b
OUTPUT SIGNALS
Figure 2. Synchronous Output Signals Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
11
CLKOUT
B13 B11 B12
TS, BB
B13a B11a B12a
TA, BI
B14 B15
TEA
Figure 3. Synchronous Active Pull-Up and Open-Drain Outputs Signals Timing Diagram
12
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B16 B17
TA, BI, TEA
B16a
B17a
TEA, RETRY, KR
B16b
B17
BB, BG, BR
Figure 4. Synchronous Input Signals Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
13
CLKOUT
B16 B17
TA
B18 B19
D(0:31), DP(0:3)
Figure 5. Input Data In Normal Case Timing Diagram
CLKOUT
TA
B20
B21
D(0:31), DP(0:3)
Figure 6. Input Data When Controlled by the UPM Timing Diagram
14
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B11 B12
TS
B8
A(6:31)
B22a B23
CSx
B25 B26
OE
B28
WE(0:3) D(0:31), DP(0:3)
B18
B19
Figure 7. External Bus Read Timing Diagram (GPCM ControlledACS = O00O)
CLKOUT
B11 B12
TS
B8
A(6:31)
B22b B22c B23
CSx
B24a
B25
B26
OE
B18
D(0:31), DP(0:3)
B19
Figure 8. External Bus Read Timing Diagram (GPCM ControlledTRLX = O0O, ACS = O10O)
MOTOROLA MPC823e ELECTRICAL SPECIFICATIONS 15
CLKOUT
B11 B12
TS
B8
A(6:31)
B22b B22c B23
CSx
B24a B26
B25
OE
B18
D(0:31), DP(0:3)
B19
Figure 9. External Bus Read Timing Diagram (GPCM ControlledTRLX = O0O, ACS = O11O)
16
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B11 B12
TS
B8
A(6:31)
B22a B23
CSx
B27 B26
OE
B27a
B18 B22b
D(0:31), DP(0:3)
B22c B19
Figure 10. External Bus Read Timing Diagram (GPCM ControlledTRLX = O1O, ACS = O10O, ACS = O11O)
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
17
CLKOUT
B11 B12
TS
B8 B30
A(6:31)
B22 B23
CSx
B25
B29b B28
WE(0:3)
B26
OE
B8
B29
D(0:31), DP(0:3)
B9
Figure 11. External Bus Write Timing Diagram (GPCM ControlledTRLX = O0O, CSNT = O0O)
18
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B11 B12
TS
B30 B8 B30a
A(6:31)
B22 B28b
B23
CSx
B28d
B25
B29c
B29g
WE(0:3)
B26 B29a B29f
OE
B8
B28a B28c
D(0:31), DP(0:3)
B9
Figure 12. External Bus Write Timing Diagram (GPCM ControlledTRLX = O0O, CSNT = O1O)
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
19
CLKOUT
B11
B12
TS
B8
B30d
B30b
A(6:31)
B28d B22
B23
CSx
B28b
B25
B29f
B29e
WE(0:3)
B26 B29h B28a B29d
OE
B29b
B8 B28c
D(0:31), DP(0:3)
B9
Figure 13. External Bus Write Timing Diagram (GPCM ControlledTRLX = O1O, CSNT = O1O)
20
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B8
A(6:31)
B31d
B31a B31 B31b
B31c
CSx
B34 B34a B34b B32d B32a B32 B32b B32c
BS_AB(0:3)
B35 B35a B35b
B33a B33
GPLA(0:5), GPLB(0:5)
B36
Figure 14. External Bus Timing Diagram (UPM-Controlled Signals)
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
21
CLKOUT
B37 B38
UPWAIT
CSx
BS_AB(0:3)
GPLA(0:5), GPLB(0:5)
Figure 15. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Diagram
22
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
B37 B38
UPWAIT
CSx
BS_AB(0:3)
GPLA(0:5), GPLB(0:5)
Figure 16. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Diagram
CLKOUT
B42 B41
TS
B40
A(6:31), TSIZ(0:1), RD/WR, BURST
B22
CSx
Figure 17. Synchronous External Master Access Timing Diagram (GPCM HandledACS = O00O)
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
23
CLKOUT
B39
AS
B40
A(6:31), TSIZ(0:1), RD/WR
B22
CSx
Figure 18. Asynchronous External Master Memory Access Timing Diagram (GPCM ControlledACS = O00O)
AS
B43
CSx, WE(0:3), BS(0:3), OE, GPLx,
Figure 19. Asynchronous External Master Timing Diagram (Control Signals Negation Time)
24
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 2. Interrupt Timing
25MHZ NUM I39 I40 I41 I42 I43 CHARACTERISTIC MIN IRQx valid to CLKOUT rising edge (setup time) IRQx hold time after CLKOUT IRQx pulse width low IRQx pulse width high IRQx edge to edge time 6 2 3 3 160 MAX N N N N N MIN 6/6 2/2 3/3 3/3 80/80 MAX N N N N N MIN 6/6 2/2 3/3 3/3 80/80 MAX N N N N N ns ns ns ns ns 40MHZ 50MHZ UNIT
NOTES: 1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The timings I41 and I42 are specied to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the MPC823e can support.
2.
CLKOUT
I39
I40
IRQx
Figure 20. Interrupt Detection Timing Diagram for External Level-Sensitive Lines
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
25
CLKOUT
I39
IRQx
I43 I41
I42
I43
Figure 21. Interrupt Detection Timing Diagram for External Edge-Sensitive Lines
26
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 3. PCMCIA Timing
25MHZ NUM P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 CHARACTERISTIC MIN A(6:31), REG valid to PCMCIA strobe asserted A(6:31), REG valid to ALE negation CLKOUT to REG valid CLKOUT to REG invalid CLKOUT to CE1, CE2 asserted CLKOUT to CE1, CE2 negated CLKOUT to PCOE, IORD, PCWE, IOWR assert time CLKOUT to PCOE, IORD, PCWE, IOWR negate time CLKOUT to ALE assert time CLKOUT to ALE negate time PCWE, IOWR negated to D(0:31) invalid WAIT_B valid to CLKOUT rising edge CLKOUT rising edge to WAIT_B invalid 28 38 10 11 10 10 N 3 10 N 8 8 2 MAX N N 19 N 19 19 12 12 19 19 N N N MIN 13 18 5 6 5 5 N 2 5 N 3 8 2 MAX N N 13 N 13 13 11 11 13 13 N N N MIN 13 18 5 6 5 5 N 2 5 N 3 8 2 MAX N N 13 N 13 13 11 11 13 13 N N N ns ns ns ns ns ns ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
NOTES: 1. 2. 3. PSST = 1. Otherwise, add PSST times cycle time. PSHT = 0. Otherwise, add PSHT times cycle time. These synchronous timings dene when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA current cycle. The WAIT_B assertion will be effective only if it is detected two cycles before the PSL timer expiration.
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
27
CLKOUT
TS
P44
A(0:31)
P45
P46
P47
REG
CE[1:2]
P50
P49
P48 P51
PCOE, PCOE, IORD
P52 P53 P52
ALE
B18
D(0:31)
B19
Figure 22. PCMCIA Access Cycles Timing Diagram (External Bus Read)
28
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT
TS
P44
A[0:31]
P45
P46
P47
REG
CE[1:2]
P50
P49
P48 P51
PCOE, IORD
P52 P53 P52
ALE
P54
D[0:31]
B8
B9
Figure 23. PCMCIA Access Cycles Timing Diagram (External Bus Write)
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
29
CLKOUT
P55
P56
WAITx
Figure 24. PCMCIA Wait Signals Detection Timing Diagram
CLKOUT
P55
P56
WAITx
Figure 25. PCMCIA Wait Signals Detection Timing Diagram
30
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 4. PCMCIA Port Timing
25MHZ NUM P57 P58 P59 P60 NOTE: CHARACTERISTIC MIN CLKOUT to OPx Valid HRESET negated to OPx drive IP_Bx valid to CLKOUT Rising Edge CLKOUT Rising Edge to IP_Bx invalid *OP2 and OP3 only. N 30 6 2 MAX 25 N N N MIN N 18 5 1 MAX 19 N N N MIN N 18 5 1 MAX 19 N N N ns ns ns ns 40MHZ 50MHZ UNIT
CLKOUT
P57
OUTPUT SIGNALS
HRESET
P58
OP2, OP3
Figure 26. PCMCIA Output Port Timing Diagram
CLKOUT
P59
P60
INPUT SIGNALS
Figure 27. PCMCIA Input Port Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
31
Table 5. Debug Port Timing
25MHZ NUM D61 D62 D63 D64 D65 D66 D67 CHARACTERISTIC MIN DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK low to DSDO invalid 120 50 0 8 5 0 0 MAX N N 3 N N 15 2 MIN 60 25 0 8 5 0 0 MAX N N 3 N N 15 2 MIN 60 25 0 8 5 0 0 MAX N N 3 N N 15 2 ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
CLKOUT
D61
D62
D62
D63
D61
D63
Figure 28. Debug Port Clock Input Timing Diagram
32
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
DSCK
D64
D65
DSDI
D66 D67
DSDO
Figure 29. Debug Port Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
33
Table 6. Reset Timing
25MHZ NUM R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 CHARACTERISTIC MIN CLKOUT to HRESET high impedance CLKOUT to SRESET high impedance RSTCONF pulse width N/A Configuration data to HRESET rising edge setup time Configuration data to RSTCONF rising edge setup time Configuration data hold time after RSTCONF negation Configuration data hold time after HRESET negation HRESET and RSTCONF asserted to data out drive RSTCONF negated to data out high impedance CLKOUT of last rising edge before chip three-states HRESET to data out high impedance DSDI and DSCK setup DSDI and DSCK hold time SRESET negated to CLKOUT rising edge for DSDI and DSCK sample 650 650 0 0 N N N 120 0 320 N N N N 25 25 25 N N N 425 425 0 0 N N N 75 0 200 N N N N 25 25 25 N N N 350 350 0 0 N N N 60 0 160 N N N N 25 25 25 N N N ns ns ns ns ns ns ns ns ns ns N N 680 MAX 20 20 N MIN N N 425 MAX 20 20 N MIN N N 340 MAX 20 20 N ns ns ns 40MHZ 50MHZ UNIT
34
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
HRESET
R71
RSTCONF
R76
R73 R75
D(0:31) (IN)
R74
Figure 30. Reset Timing Diagram (Configuration from Data Bus)
CLKOUT
R69
HRESET
RSTCONF
R78
R77 R79
D(0:31) (OUT) (WEAK)
Figure 31. Reset Timing DiagramMPC823e Data Bus Weak Drive During Configuration
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
35
CLKOUT
R70 R82
SRESET
R80 R80
R81
R81
DSCK, DSDI
Figure 32. Reset Timing DiagramDebug Port Configuration
36
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 7. JTAG Timing
25MHZ NUM J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 J92 J93 J94 J95 J96 TCK cycle time TCK clock pulse width measured at 1.5V TCK rise and fall times TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to output valid TCK falling edge to ouput valid out of high impedance TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge TCK rising edge to boundary scan input invalid CHARACTERISTIC MIN 100 40 0 5 25 N 0 N 100 40 N N N 50 50 MAX N N 10 N N 27 N 20 N N 50 50 50 N N MIN 100 40 0 5 25 N 0 N 100 40 N N N 50 50 MAX N N 10 N N 27 N 20 N N 50 50 50 N N MIN 100 40 0 5 25 N 0 N 100 40 N N N 50 50 MAX N N 10 N N 27 N 20 N N 50 50 50 N N ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
TCK
J84 J82 J83 J83
J84
J82
Figure 33. JTAG Test Clock Input Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
37
TCK
J85 J86
TMS, TDI
J87 J89 J88
TDO
Figure 34. JTAGTest Access Port Timing Diagram
TCK
J91 J90
TRST
Figure 35. JTAGTRST Timing Diagram
38
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
TCK
J92 J94
OUTPUT SIGNALS
J93
OUTPUT SIGNALS
J96
J95
OUTPUT SIGNALS
Figure 36. Boundary Scan (JTAG) Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
39
COMMUNICATION ELECTRICAL CHARACTERISTICS
Table 8. Parallel Input/Output Port Timing
25MHZ NUM 29 30 31 CHARACTERISTIC MIN Data-in setup time to clock high Data-in hold time from clock high Clock high to data-out valid (CPU writes data, control, or direction) 20 10 N MAX N N 25 MIN 15 7.5 N MAX N N 25 MIN 15 7.5 N MAX N N 25 ns ns ns 40MHZ 50MHZ UNIT
CLKOUT
29 30
DATA IN
31
DATA OUT
Figure 37. Parallel Input/Output Data-In/Data-Out Timing Diagram
40
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 9. IDMA Timing
25MHZ NUM 40 41 42 43 44 45 46 CHARACTERISTIC MIN DREQ setup time to clock high DREQ hold time from clock high SDACK assertion delay from clock high SDACK negation delay from clock low SDACK negation delay from TA low SDACK negation delay from clock high TA assertion to falling edge of the clock setup time 12 5 N N N N 12 MAX N N 20 20 25 20 N MIN 7 3 N N N N 7 MAX N N 12 12 20 15 N MIN 7 3 N N N N 7 MAX N N 12 12 20 15 N nsec nsec nsec nsec nsec nsec nsec 40MHZ 50MHZ UNIT
NOTE: Applies to external TA.
CLKOUT (OUTPUT)
41
DREQ (INPUT)
40
Figure 38. IDMA External Requests Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
41
CLKOUT (OUTPUT)
TS (OUTPUT)
RD / WR (OUTPUT)
42 43
DATA
46
TA (OUTPUT)
SDACK
Figure 39. SDACK Timing DiagramPeripheral Write, TA Sampled Low at the Falling Edge of the Clock
42
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLKOUT (OUTPUT)
TS (OUTPUT)
RD / WR (OUTPUT)
42 44
DATA
TA (OUTPUT)
SDACK
Figure 40. SDACK Timing DiagramPeripheral Write, TA Sampled High at the Falling Edge of the Clock
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
43
CLKOUT (OUTPUT)
TS (OUTPUT)
RD / WR (OUTPUT)
42 45
DATA
TA (OUTPUT)
SDACK
Figure 41. SDACK Timing DiagramPeripheral Read
44
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 10. Baud Rate Generator Timing
25MHZ NUM 50 51 52 CHARACTERISTIC MIN BRGO rise and fall times BRGO duty cycle BRGO cycle N 40 40 MAX 10 60 N MIN N 40 40 MAX 10 60 N MIN N 40 40 MAX 10 60 N ns % ns 40MHZ 50MHZ UNIT
50
50
BRGOx
51 52 51
Figure 42. Baud Rate Generator Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
45
Table 11. General-Purpose Timers Timing
25MHZ NUM 61 62 63 64 65 CHARACTERISTIC MIN TIN/TGATE rise and fall times TIN/TGATE low time TIN/TGATE high time TIN/TGATE cycle time CLKO low to TOUT valid 12 5 N N N MAX 10 1 20 20 25 MIN 7 3 N N N MAX 10 1 12 12 20 MIN 7 3 N N N MAX 10 1 12 12 20 ns clk clk clk ns 40MHZ 50MHZ UNIT
60
CLKOUT
61
63
62
TIN / TGATE (INPUT)
61 64
TOUT (OUTPUT)
65
Figure 43. General-Purpose Timers Timing Diagram
46
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 12. Serial Interface Timing
25MHZ NUM CHARACTERISTIC MIN 70 71 71a 72 73 74 75 76 77 78 78a 79 80 80a 81 82 83 83a 84 85 86 87 88 L1RCLK and L1TCLK frequency (DSC=0)1,3 L1RCLK and L1TCLK width low (DSC=0)3 L1RCLK and L1TCLK width high (DSC=0)2 L1TXD, L1ST(18), L1RQ, L1CLKO rise and fall times L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) L1CLK edge to L1RSYNC and L1TSYNC invalid (SYNC hold time) L1RSYNC and L1TSYNC rise and fall times L1RXD valid to L1CLK edge (L1RXD setup time) L1CLK edge to L1RXD invalid (L1RXD hold time) L1CLK edge to L1ST(18) valid L1SYNC valid to L1ST(18) valid4 L1CLK edge to L1ST(18) invalid L1CLK edge to L1TXD valid L1TSYNC valid to L1TXD valid4 L1CLK edge to L1TXD high impedance L1RCLK and L1TCLK frequency (DSC=1) L1RCLK and L1TCLK width low (DSC=1) L1RCLK and L1TCLK width high (DSC=1)2 L1CLK edge to L1CLKO valid (DSC=1) L1RQ valid before falling edge of L1TSYNC3 L1GR setup time3 L1GR hold time3 L1CLK edge to L1SYNC valid (FSD = 00, CNT = 0000, BYT = 0, DSC=0) N P+10 P+10 N 20 35 N 42 35 10 10 10 10 10 0 N P+10 P+10 N 1 42 42 N MAX 10 N N 15 N N 15 N N 45 45 45 65 65 42 12.5 N N 30 N N N 0 MIN N P+10 P+10 N 20 35 N 42 35 10 10 10 10 10 0 N P+10 P+10 N 1 42 42 N MAX 10 N N 15 N N 15 N N 45 45 45 65 65 42 16 N N 30 N N N 0 MIN N P+10 P+10 N 20 35 N 42 35 10 10 10 10 10 0 N P+10 P+10 N 1 42 42 N MAX 10 N N 15 N N 15 N N 45 45 45 65 65 42 16 N N 30 N N N 0 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns L1TCLK ns ns ns 40MHZ 50MHZ UNIT
NOTES: 1. 2. 3. 4. The ratio SyncCLK/L1RCLK must be greater than 2.5/1. Where P=1/CLKO1. For a 25MHz CLKO1 rate, P=40ns. These electrical specications are only valid for IDL mode. The strobes and TXD2 on the rst bit of the frame becomes valid after L1CLK edge or L1SYNC, whichever is later.
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
47
71
70
L1RCLK (FE=0, CE=0) (INPUT)
72
L1RCLK (FE=1, CE=1) (INPUT)
75
RFCD=1 L1RSYNC (INPUT)
73 74 77
L1RXD (INPUT)
76
BIT0
L1ST(1-4) (OUTPUT)
78 79
Figure 44. Serial Interface Receive Timing Diagram With Normal Clocking (DSC =0)
48
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
70
L1TCLK (FE=0, CE=0) (INPUT)
71
72
L1TCLK (FE=1, CE=1) (INPUT)
73 75
L1TSYNC (INPUT)
74
TFCD=0
80a 81
L1TXD (OUTPUT)
80
BIT0
78a
79
L1ST(1-4) (OUTPUT)
78
Figure 45. Serial Interface Transmit Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
49
Table 13. Serial Communication Controller in NMSI External Timing
25MHZ NUM 100 101 102 103 104 105 106 107 108 CHARACTERISTIC MIN RCLK1 and TCLK1 width high1 RCLK1 and TCLK1 width low RCLK1 and TCLK1 rise and fall times TXD2 active delay (from TCLK1 falling edge) RTS1 active/inactive delay (from TCLK1 falling edge) CTS1 setup time to TCLK1 rising edge RXD2 setup time to RCLK1 rising edge RXD2 hold time from RCLK1 rising edge2 CD1 setup time to RCLK1 rising edge CLKOUT F CLKOUT +5ns N 0 0 5 5 5 5 MAX N N 15 50 50 N N N N MIN CLKOUT F CLKOUT +5ns N 0 0 5 5 5 5 MAX N N 15 50 50 N N N N MIN CLKOUT F CLKOUT +5ns N 0 0 5 5 5 5 MAX N N 15 50 50 N N N N MHz ns ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
NOTES: 1. 2. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1. Applies to CD and CTS hold time when they are used as external sync signals.
50
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 14. Serial Communication Controller in NMSI Internal Timing
25MHZ NUM 100 102 103 104 105 106 107 108 NOTES: 1. 2. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1. Applies to CD and CTS hold time when they are used as external sync signals. CHARACTERISTIC MIN RCLK1 and TCLK1 frequency1 RCLK1 and TCLK1 rise and all times TXD2 active delay (from TCLK1 falling edge) RTS1 active/inactive delay (from TCLK1 falling edge) CTS1 setup time to TCLK1 rising edge RXD2 setup time to RCLK1 rising edge RXD2 hold time from RCLK1 rising edge2 CD1 setup time to RCLK1 rising edge 0 N 0 0 40 40 0 40 MAX 8.3 N 30 30 N N N N MIN 0 N 0 0 40 40 0 40 MAX 13 N 30 30 N N N N MIN 0 N 0 0 40 40 0 40 MAX 16 N 30 30 N N N N MHz ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
102
102
101
RCLK1
100 106
RXD2 (INPUT)
107 108
CD1 (INPUT)
107
CD1
(SYNC
INPUT)
Figure 46. SCC NMSI Receive Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
51
102
101
TCLK1
102 103 100
TXD2 (OUTPUT)
105
RTS1 (OUTPUT)
104 104
CTS1 (INPUT)
107
CTS1 (SYNC INPUT)
Figure 47. SCC NMSI Transmit Timing Diagram
52
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
102
101
TCLK1
102 103 100
TXD2 (OUTPUT)
104
RTS1 (OUTPUT)
107 105 104
CTS1 (ECHO INPUT)
Figure 48. HDLC Bus Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
53
Table 15. Ethernet Timing
25MHZ NUM 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 NOTES: 1. 2. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1. SDACK is asserted when the SDMA writes the incoming frame DA into memory. CHARACTERISTIC MIN CLSN (CTS2) width high RCLK1 rise and fall times RCLK1 width low RCLK1 clock period1 RXD2 setup time RXD2 hold time RENA (CD2) active delay (from RCLK1 rising edge of the last data bit) RENA (CD2) width low TCLK1 rise and fall times TCLK1 width low TCLK1 clock period1 TXD2 active delay (from TCLK1 rising edge) TXD2 inactive delay (from TCLK1 rising edge) TENA (RTS2) active delay (from TCLK1 rising edge) TENA (RTS2) inactive delay (from TCLK1 rising edge) N/A N/A N/A CLKx low to SDACK asserted2 CLKx low to SDACK negated3 N N 20 20 N N 20 20 N N 20 20 ns ns 40 N 40 80 20 5 10 100 N 40 99 10 10 10 10 MAX N 15 N 120 N N N N 15 N 101 50 50 50 50 MIN 40 N 40 80 20 5 10 100 N 40 99 10 10 10 10 MAX N 15 N 120 N N N N 15 N 101 50 50 50 50 MIN 40 N 40 80 20 5 10 100 N 40 99 10 10 10 10 MAX N 15 N 120 N N N N 15 N 101 50 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
54
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
CLSN (CTS1) (INPUT)
120
Figure 49. Ethernet Collision Timing Diagram
121
121
RCLK1
124 123
RXD2 (INPUT)
125
LAST BIT
127
RENA (CD1) (INPUT)
126
Figure 50. Ethernet Receive Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
55
128
128 129
TCLK1
121 131 132
TXD2 (OUTPUT)
133
134
TENA (RTS1) (INPUT)
RENA (CD1) (INPUT) (NOTE 2) NOTES: 1. TRANSMIT CLOCK INVERT (TCI) BIT IN THE GSMR IS SET. 2. IF RENA IS DEASSERTED BEFORE TENA, OR RENA IS NOT ASSERTED AT ALL DURING TRANSMIT, THEN THE CSL BIT IS SET IN THE BUFFER DESCRIPTOR AT THE END OF FRAME TRANSMISSION.
Figure 51. Ethernet Transmit Timing Diagram
56
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 16. Serial Peripheral Interface Master Timing
25MHZ NUM 160 161 162 163 164 165 166 167 CHARACTERISTIC MIN Master cycle time Master clock (SCK) high or low time Master data setup time (inputs) Master data hold time (inputs) Master data valid (after SCK edge) Master data hold time (outputs) Rise time output Fall time output 4 2 50 0 N 0 N N MAX 1,024 512 N N 20 N 15 15 MIN 4 2 50 0 N 0 N N MAX 1,024 512 N N 20 N 15 15 MIN 4 2 50 0 N 0 N N MAX 1,024 512 N N 20 N 15 15 tcyc tcyc ns ns ns ns ns ns 40MHZ 50MHZ UNIT
NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1.
160 161 161 167 166
SPICLK CI=0 (OUTPUT)
163 167
SPICLK CI=1 (OUTPUT)
166 162
SPIMISO (INPUT)
MSB IN
DATA
LSB IN
164
MSB IN
165
SPIMOSI (OUTPUT)
MSB OUT
167
DATA
LSB OUT
166
MSB OUT
Figure 52. SPI Master (CP=0) Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
57
160 161 161 167 166
SPICLK CI=0 (OUTPUT)
163 167
SPICLK CI=1 (OUTPUT)
166 162
SPIMISO (INPUT)
MSB IN
DATA
164 165
LSB IN
MSB IN
SPIMOSI (OUTPUT)
MSB OUT
167
DATA
LSB OUT
166
MSB OUT
Figure 53. SPI Master (CP=1) Timing Diagram
58
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 17. Serial Peripheral Interface Slave Timing
25MHZ NUM 170 171 172 173 174 175 176 177 178 179 180 181 182 CHARACTERISTIC MIN Slave cycle time Slave enable lead time Slave enable lag time Slave clock (SPICLK) high or low time Slave sequential transfer delay (does not require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time Slave SPI MISO disable time Slave data valid (after SPICLK edge) Slave data hold time (outputs) Rise time (input) Fall time (input) 2 15 15 1 1 20 20 N N N 0 N N MAX N N N N N N N 50 50 50 N 15 15 MIN 2 15 15 1 1 20 20 N N N 0 N N MAX N N N N N N N 50 50 50 N 15 15 MIN 2 15 15 1 1 20 20 N N N 0 N N MAX N N N N N N N 50 50 50 N 15 15 tcyc ns ns tcyc tcyc ns ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
59
172
171
SPISEL (INPUT)
173 173 182 170 181 174
SPICLK CI=0 (INPUT)
SPICLK CI=1 (INPUT)
177 180 181 182 178
SPIMISO (OUTPUT)
175
MSB OUT
DATA
179
LSB OUT
UNDEF
MSB OUT
176
SPIMOSI (INPUT)
MSB IN
DATA
182
LSB IN
181
MSB IN
Figure 54. SPI Slave (CP=0) Timing Diagram
60
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
172
SPISEL (INPUT)
173 173 170 182 174
SPICLK CI=0 (INPUT)
171 181 181
SPICLK CI=1 (INPUT)
182 177 180 178
SPIMISO (OUTPUT)
UNDEF
175
MSB OUT
179 176
DATA
LSB OUT
MSB OUT
SPIMOSI (INPUT)
MSB IN
182
DATA
181
LSB IN
MSB IN
Figure 55. SPI Slave (CP=1) Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
61
Table 18. I2C TimingNSCL < 100 kHz
25MHZ NUM 200 200 202 203 204 205 206 207 208 209 210 211 CHARACTERISTIC MIN SCL clock frequency (slave) SCL clock frequency (master) Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time STOP condition setup time 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 N N 4.7 MAX 100 100 N N N N N N N 1 300 N MIN 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 N N 4.7 MAX 100 100 N N N N N N N 1 300 N MIN 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 N N 4.7 MAX 100 100 N N N N N N N 1 300 N kHz kHz ms ms ms ms ms ms ns ms ns ms 40MHZ 50MHZ UNIT
NOTE: SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) * pre_scaler * 2 ). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater than or equal to 4/1.
Table 19. I2C TimingNSCL > 100 kHz
NUM 200 200 202 203 204 205 206 207 208 209 210 211 CHARACTERISTIC SCL clock frequency (slave) SCL clock frequency (master) Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time MINIMUM 0 BRGCLK/16512 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 0 1/(40 * fSCL) N N 1/(2.2 * fSCL) MAXIMUM BRGCLK/48 BRGCLK/48 N N N N N N N 1/(10 * fSCL) 1/(33 * fSCL) N UNIT Hz Hz sec sec sec sec sec sec sec sec sec sec
62
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
SDA
202 203 204
205
207
208
SCL
209 206 210 211
Figure 56. I2C Bus Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
63
Table 20. Serial Management Controller Timing
25MHZ NUM 150 151 151A 152 153 154 155 CHARACTERISTIC MIN CLK1 clock period CLK1 width low CLK1 width high CLK1 rise and fall times SMTXDx active delay (from CLK1 falling edge) SMRXDx/SYNC1 setup time SMRXDx/SYNC1 hold time 100 50 50 N 10 20 5 MAX N N N 15 50 N N MIN 100 50 50 N 10 20 5 MAX N N N 15 50 N N MIN 100 50 50 N 10 20 5 MAX N N N 15 50 N N ns ns ns ns ns ns ns 40MHZ 50MHZ UNIT
NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1.
152 152 151 161a
SMCLK
150
SMTXDX (OUTPUT)
154
*
155
153
SYNC1
154 155
SMRXDX (INPUT)
NOTE: * THIS DELAY IS EQUAL TO AN INTEGER NUMBER OF OCHARACTER LENGTHO CLOCKS.
Figure 57. SMC Transparent Timing Diagram
64
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
Table 21. LCD Controller Timing
25MHZ NUM 220 221 223 224 225 226 227 228 229 230 231 232 233 234 235 236 NOTES: 1. 2. 3. 4. T = shift clock cycle (220). This number is given for wbl(wait between lines) 2. For wbl=n {n>2} the timing will be (n+2)T. This number is given for wbl(wait between lines) 2. For wbl=n {n>2} the timing will be (n+2)T. Wait Between Frames (WBF) is a programmable parameter. CHARACTERISTIC MIN Shift clock cycle time Shift clock high time CLOCK/HSYNC/VSYNC/OE rise and fall times Data valid delay from shift clock high VSYNC to HSYNC setup time1 VSYNC hold time HSYNC pulse width Time from clock falling edge to HSYNC rising edge Time from HSYNC falling edge to clock rising edge2 AC active delay VSYNC pulse width (TFT) HSYNC to OE delay3 OE to HSYNC delay VSYNC to OE delay (TFT) VSYNC/HSYNC/OE active delay (TFT) Wait between frames4 40 20 N N 5 1 4 4.5 4 N 1 4 4 0 N WBF MAX N N 10 15 N N N N N 25 16 N N 1,023 15 N MIN 40 20 N N 5 1 4 4.5 4 N 1 4 4 0 N WBF MAX N N 10 15 N N N N N 25 16 N N 1,023 15 N MIN 40 20 N N 5 1 4 4.5 4 N 1 4 4 0 N WBF MAX N N 10 15 N N N N N 25 16 N N 1,023 15 N nsec nsec nsec nsec T T T T T nsec Line T T T nsec Line 40MHZ 50MHZ UNIT
Tcyc is the cycle time of the LCD clock (shift clock). Tdelay is a circuit delay that is specified in the AC electrical specifications. 116 lines is a time period that can vary between one scan line and 16, depending on how the LCD controller is programmed in the VPW field of the LCVCR. 01,023 lines is a time period that can vary between 0 and 1,023 scan lines in the WBF field of the LCVCR.
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
65
223 223 224 221
220
SHIFT CLOCK
DATA
228 225
227
229
SHIFT CLOCK
226
HSYNC
VSYNC
LCD_AC
230
NTH LINE VSYNC
236
FIRST LINE
SECOND LINE
HSYNC
SHIFT CLOCK
Figure 58. Passive Panel Timing Diagram
66
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
227
233
235
224
SHIFT
DATA
235
OE
232
231
234
HSYNC
VSYNC
225
OE
NTH LINE VSYNC
235
FIRST LINE
HSYNC
OE
Figure 59. TFT Panel Timing Diagram
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
67
Table 22. Video Controller Timing
25MHZ NUM 240 241 242 243 CHARACTERISTIC MIN Clock cycle time Clock high time CLK/HSYNC/VSYNC/BLANK/FIELD rise and fall times Clock high to data valid 32 13 N 10 MAX N N 10 25 MIN 32 13 N 10 MAX N N 10 25 MIN 32 13 N 10 MAX N N 10 25 nsec nsec nsec nsec 40MHZ 50MHZ UNIT
242 242 240
243
241
CLK
DATA HSYNC VSYNC FIELD BLANK
Figure 60. Video Controller Timing
68
MPC823e ELECTRICAL SPECIFICATIONS
MOTOROLA
MOTOROLA
MPC823e ELECTRICAL SPECIFICATIONS
69
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

▲Up To Search▲

Price & Availability of MPC823EELD

	To Download MPC823EELD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .